1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and more particularly, to a synchronous semiconductor memory device with improved latency control.
2. Description of the Related Art
A synchronous semiconductor memory device inputs/outputs data in synchronization with an external clock signal. Since the external interface of the synchronous semiconductor memory device is synchronized with the external clock signal, it is possible to set it beforehand so that the clock cycle effective data can be output after a controller orders a read command.
CAS latency refers to a period of time from when a read command or a column address is input to a synchronous semiconductor memory device until a time when data is output. The CAS latency is generally expressed as a multiple of an external clock cycle tCC. That is, when the read command (the column address supplied together with the read command) is received, data is output from the synchronous semiconductor memory device after a number of clock cycles corresponding to the CAS latency pass. For example, assuming that the CAS latency is 5, data should be output in synchronization with an external clock cycle generated after five clock cycles from an external clock cycle from which a read command is applied.
Therefore, the synchronous semiconductor memory device should read out data in response to the read command and then output the data after predetermined clock cycles, that is, clock cycles corresponding to the set CAS latency.
A latency circuit generates a latency signal for controlling the CAS latency so that data can be output after predetermined clock cycles in the synchronous semiconductor memory device. The latency circuit internally uses a transfer clock signal and a sampling clock signal in order to generate the latency signal. The transfer clock signal is a clock signal generated in synchronization with a data output clock signal that is obtained by passing an external clock signal through a variable delay circuit DLL. In addition, the sampling clock signal is a clock signal obtained by buffering the external clock signal and passing the external clock signal through another variable delay circuit. A predetermined time difference should be maintained between the transfer clock signal and the sampling clock signal. However, in the synchronous semiconductor memory device operating at a high-frequency, an early-stage operation of a variable delay circuit may not be stable. Accordingly, it is difficult to maintain the predetermined time difference between the transfer clock signal and the sampling clock signal which have passed through different variable delay circuits. As a result, an operational failure may occur in the synchronous semiconductor memory device.